This invention relates to an improved means for electrically connecting at least two components by means of a solder element. The improved means reduces the effect of thermal and mechanical stress on the join of the two components in comparison to conventional techniques.
Wafer Level Chip Scale Packages (WLCSPs) are used to connect a printed circuit board (PCB) to an integrated circuit (IC) chip. Commonly a WLCSP comprises at least one dielectric layer having solder elements on a first side. These solder elements are electrically connected to an IC chip on a second side of the dielectric by means of conductive traces extending through the layer. The solder elements can then be used for connection to a PCB or other substrate. Sometimes, multiple dielectric layers can be used. In this case, the IC chip is attached to a first dielectric layer and the solder element is attached to a second dielectric layer. Also, sometimes the pattern of the IC chip pads can be redistributed using the dielectric layer(s) and a conductive interconnection layer so that the solder elements on the first side form a standard array for interconnection.
However, the connection of the WLCSP to the PCB at the solder element join is not always reliable as the join is susceptible to failure from both mechanical and thermal stress. This failure could either occur in the join itself or in either the IC chip or the WLCSP if the stress is transmitted through the join. Failure by means of mechanical stress can be caused by mechanical vibrations in the device (from, for example, dropping the device). The susceptibility of the system to failure can be exacerbated when the IC technology requires the addition of low k dielectric layers. Low k dielectrics currently being used in this area can be brittle. The main source of thermal stress arises in mismatches in the coefficient of thermal expansion (CTE) between the IC and the PCB to which it is attached.
Several techniques are currently being implemented to reduce the amount of failures due to these kinds of stress.
One technique, which is the subject of pending US patent publication number US 2010/0013093, can involve adjusting the polymer materials and the thicknesses of the polymer layers to reduce the effect of stress.
Another option would be to use a modified solder composition which has an improved resistance to failure under stress.
Both of these techniques involve the specific selection of materials to be used.